1. Technical Field
The present invention relates to memory devices and semiconductor devices. In particular, the present invention relates to memory circuits that can readily read stored data, and semiconductor devices equipped with the memory circuits.
2. Related Art
JP-A-64-66899 describes a memory cell that is equipped with a static cell having two internal nodes and a nonvolatile section having two ferroelectric capacitors. When a voltage that inverts the polarity of the ferroelectric capacitors is applied to the ferroelectric capacitors, the voltage at one of the internal nodes becomes slightly higher than the voltage at the other internal node. As a result, data is transferred from the nonvolatile section to the static cell.
However, when data is transferred from the nonvolatile section to the static cell in the memory cell described above, the bit line needs to be pre-charged, and further the voltage needs to be applied to the ferroelectric capacitors, which causes a problem in that the operations become complex. When the memory cell is used in a program circuit, data must be determined immediately after the power turns on, and therefore a circuit for detecting the power-on and a control circuit for performing the operations are required. Moreover, because a control signal is generated for the operations after detecting the power-on, it takes some time for determining data. Also, in the memory cell described above, although the voltage at one of the internal nodes becomes higher than the voltage at the other internal node, their voltage difference is very small, which causes a problem in that the static cell may malfunction when manufacturing differences are present in the threshold voltages of transistors that compose the static cell.